题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);

reg     [1:0]   bit_cnt;
reg     [7:0]   data_reg;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        bit_cnt <=  2'd0;
    else    if(valid_in && bit_cnt==2'd2)
        bit_cnt <=  2'd0;
    else    if(valid_in)
        bit_cnt <=  bit_cnt + 1'b1;



always@(posedge clk or negedge rst_n)
    if(!rst_n)
        valid_out   <=  1'b0;
    else    if(bit_cnt!=2'd0 && valid_in)
        valid_out   <=  1'b1;
    else
        valid_out   <=  1'b0;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        data_reg    <=  8'd0;
    else 
        data_reg    <=  data_in;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        data_out    <=  12'd0;
    else    if(bit_cnt==2'd1 && valid_in)
        data_out    <=  {data_reg,data_in[7:4]};
    else    if(bit_cnt==2'd2 && valid_in)
        data_out    <=  {data_reg[3:0],data_in};




endmodule