题解 | #RAM的简单实现#
RAM的简单实现
https://www.nowcoder.com/practice/2c17c36120d0425289cfac0855c28796
`timescale 1ns/1ns
module ram_mod(
input clk,
input rst_n,
input write_en,
input [7:0] write_addr,
input [3:0] write_data,
input read_en,
input [7:0] read_addr,
output reg [3:0] read_data
);
//prameter
parameter WIDTH = 4;
parameter DEPTH = 8;
reg [WIDTH-1:0] MEM [DEPTH-1:0];
//写数据到RAM
genvar i;
generate for(i=0 ; i < DEPTH ; i=i+1)
begin:RAM
always@(posedge clk or rst_n)begin
if(!rst_n)
MEM[i]<=0;
else if(write_en)
MEM[write_addr]<= write_data;
end
end
endgenerate
//数据从RAM读出数据
always@(posedge clk or rst_n)begin
if(!rst_n)
read_data<=0;
else if(read_en)
read_data<=MEM[read_addr];
end
endmodule
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