题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
//独热码
	parameter s0 = 4'b0001;
	parameter s1 = 4'b0010;
	parameter s2 = 4'b0100;
	parameter s3 = 4'b1000;

reg [3:0] curr_state;
reg [3:0] next_state;

//计数器，有四个数所以计数到3置零；
/*
reg [1:0] cnt;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		cnt <= 2'd0;
	end
	else if(data_valid)begin
		if(cnt==2'd3)
			cnt <= 2'd0;
		else 
			cnt <= cnt + 1'b1;
	end
end
*/

//FSM 1 step
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		curr_state <= s0;
	end
	else 
		curr_state <= next_state;
end
//FSM 2 step
always@(*)begin
	case(curr_state)
		s0:
		if(data_valid)begin
			if(data==0)
				next_state = s1;
			else
				next_state = s0;
		end
		else 
			next_state = s0;
		s1:
		if(data_valid)begin
			if(data==1)
				next_state = s2;
			else
				next_state = s1;
		end
		else 
			next_state = s1;

		s2:
		if(data_valid)begin
			if(data==1)
				next_state = s3;
			else
				next_state = s2;
		end
		else 
			next_state = s2;

		s3:
		if(data_valid)begin
			if(data==0)
				next_state = s0;
			else
				next_state = s3;
		end
		else 
			next_state = s3;
		
		default:next_state = s0;
		endcase	
end




always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		match <= 1'b0;
	else if(curr_state == s3)begin
		match <= 1'b1;
	end
	else
		match <= 1'b0;
end

endmodule