`timescale 1ns/1ns module mux( input clk_a , input clk_b , input arstn , input brstn , input [3:0] data_in , input data_en , output reg [3:0] dataout ); reg data_en_r1,data_en_r2,data_en_r3; reg [3:0] data_in_reg; always@(posedge clk_a or negedge arstn)...