题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//
reg [2:0] cnt;
reg clk_out7_reg; 
always@(posedge clk_in or negedge clk_in or negedge rst)
if(!rst) cnt<=0;
else if(cnt==6) cnt<=0;else cnt<=cnt+1;

always@(posedge clk_in or negedge clk_in or negedge rst)
if(!rst) clk_out7_reg<=0;
else if(cnt==6) clk_out7_reg<=~clk_out7_reg;

assign clk_out7=clk_out7_reg;

//*************code***********//
endmodule