题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
reg flag;
reg [1:0] cnt;
reg [7:0]		   data_in_reg;

always@(posedge clk or negedge rst_n)
if(!rst_n) data_in_reg<=0;
else if(valid_in) data_in_reg<=data_in;


always@(posedge clk or negedge rst_n)
if(!rst_n) cnt<=0;
else if(valid_in) cnt <= (cnt==2) ? 0 :  cnt+1;



always@(posedge clk or negedge rst_n)
if(!rst_n) flag<=0;
else if(valid_in) flag<=~flag;


always@(posedge clk or negedge rst_n)
if(!rst_n) valid_out<=0;
else if(valid_in && flag==1) valid_out<=1;
else valid_out<=0;

always@(posedge clk or negedge rst_n)
if(!rst_n) data_out<=0;
else if(valid_in && flag==1) data_out<={data_in_reg,data_in};

endmodule