题解 | 实现3-8译码器①

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);

wire    Y0_m   ,  
        Y1_m   , 
        Y2_m   , 
        Y3_m   , 
        Y4_m   , 
        Y5_m   , 
        Y6_m   , 
        Y7_m   ;

and and0(Y0_m,E3,~E2_n,~E1_n,~A2,~A1,~A0);
and and1(Y1_m,E3,~E2_n,~E1_n,~A2,~A1, A0);
and and2(Y2_m,E3,~E2_n,~E1_n,~A2, A1,~A0);
and and3(Y3_m,E3,~E2_n,~E1_n,~A2, A1, A0);
and and4(Y4_m,E3,~E2_n,~E1_n, A2,~A1,~A0);
and and5(Y5_m,E3,~E2_n,~E1_n, A2,~A1, A0);
and and6(Y6_m,E3,~E2_n,~E1_n, A2, A1,~A0);
and and7(Y7_m,E3,~E2_n,~E1_n, A2, A1, A0);

assign Y0_n = ~Y0_m ;
assign Y1_n = ~Y1_m ;
assign Y2_n = ~Y2_m ;
assign Y3_n = ~Y3_m ;
assign Y4_n = ~Y4_m ;
assign Y5_n = ~Y5_m ;
assign Y6_n = ~Y6_m ;
assign Y7_n = ~Y7_m ;

endmodule