题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

	parameter s0 = 'd0;
	parameter s1 = 'd1;
	parameter s2 = 'd2;
	parameter s3 = 'd3;
	parameter s4 = 'd4;
	parameter s5 = 'd5;
	parameter fail = 'd6;

	reg [2:0]	state,nstate;
	reg [2:0]	cnt;

	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)
			cnt <= 'd0;
		else if(cnt == 'd5)
			cnt <= 'd0;
		else
			cnt <= cnt + 'd1; 
	end

	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)
			state <= s0;
		else
			state <= nstate;
	end

	always@(*)begin
		if(!rst_n)
			nstate = s0;
		else begin
			case(state)
			s0:begin
				if(data == 'd0)
					nstate = s1;
				else
					nstate = fail;
			end

			s1:begin
				if(data == 'd1)
					nstate = s2;
				else
					nstate = fail;
			end

			s2:begin
				if(data == 'd1)
					nstate = s3;
				else
					nstate = fail;
			end

			s3:begin
				if(data == 'd1)
					nstate = s4;
				else
					nstate = fail;
			end

			s4:begin
				if(data == 'd0)
					nstate = s5;
				else
					nstate = fail;
			end

			s5:begin
				nstate = s0;
			end
			default:nstate = s0;
		endcase
		end
	end

	always@(posedge clk,negedge rst_n)begin
		if(!rst_n)begin
			match <= 'd0;
			not_match <= 'd0;
		end
		else if(cnt == 'd5)begin
			if(state == s5 && data == 'd0)begin
				match <= 'd1;
				not_match <= 'd0;
			end
			else begin
				match <= 'd0;
				not_match <= 'd1;
			end
		end
		else begin
			match <= 'd0;
			not_match <= 'd0;
		end
	end



endmodule