题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter s0=3'd0, s1=3'd1,s2=3'd2,s3=3'd3;

reg [1:0]current_state,next_state;

always@(*)
begin
case(current_state)
3'd0:next_state=data ? s1 :s0;
3'd1:next_state= data ? s2: s1;
3'd2:next_state= data ? s3: s2;
3'd3:next_state= data ? s0: s3;
default :next_state= s0;
endcase
end

	always@(posedge clk or negedge rst)
	begin
	if(!rst)
	begin
	current_state<=s0;
	end
	else
	begin
	current_state<=next_state;
	end
	end

		always@(posedge clk or negedge rst)
		begin
		if(!rst)
		begin
		flag=1'b0;
		end
		else
		begin
		flag=(current_state==s3 && next_state==s0);
		end
		end
//*************code***********//
endmodule