题解 | #模拟逻辑芯片#

`timescale 1ns/1ns

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

 wire temp0,temp1,temp2,temp3;
assign temp0=p2a&p2b,  temp1=p1a&p1c&p1b,  temp2=p1f&p1e&p1d, temp3=p2c&p2d;
assign p2y=temp0|temp3;
assign p1y=temp1|temp2;

endmodule