题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
reg [3:0] data_areg;
reg data_en_breg;
always@(posedge clk_a or negedge arstn) begin
	if(~arstn) data_areg <= 0;
	else data_areg <= data_in;
end
always@(posedge clk_a or negedge arstn) begin
	if(~arstn) data_en_breg <= 0;
	else data_en_breg <= data_en;
end

// clock b
reg data_en_areg1,data_en_areg2;
always@(posedge clk_b or negedge brstn) begin
	if(~brstn) begin
		data_en_areg1 <= 0;
		data_en_areg2 <= 0;
	end
	else begin
		data_en_areg2 <= data_en_breg;
		data_en_areg1 <= data_en_areg2;
	end
end
always@(posedge clk_b or negedge brstn) begin
	if(~brstn) dataout <= 0;
	else dataout <= (data_en_areg1)? data_areg : dataout;
end
endmodule