题解 | #加减计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input mode,
	output reg [3:0]number,
	output reg zero
	);

	reg [3:0] num;
	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			num <= 'd0;
		else if(mode == 1'b1)begin
			if(num == 'd9)
				num <= 'd0;
			else
				num <= num + 1'b1;
		end
		else if(mode == 1'b0) begin
			if(num == 'd0)
				num <= 'd9;
			else
				num <= num - 1'b1;
		end
		else
			num <= num;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			number <= 'd0;
		else
			number <= num;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			zero <= 1'b0;
		else if(num == 'd0)
			zero = 1'b1;
		else	
			zero = 1'b0;
	end
endmodule

zero输出和时序图有歧义，答案要求只要number输出0zero就拉高，但题目给的时序图，在rst_n刚拉高时，number为0，zero并没有拉高。