题解1 | #优先编码器电路①#

不知道为啥第二Y_n[2] 前面写个assign就给我报错 QAQ

真值表写等式的时候注意写出来的是1，要取反得到Y_n

`timescale 1ns/1ns

module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);


always @(*)(1444584)
begin
assign Y_n[3] = ~(~I_n[8] || ~I_n[7]);

Y_n[2] = ~( (& I_n[8:7]) & (~I_n[6] || ~I_n[5] || ~I_n[4] || ~I_n[3]));

assign Y_n[1] = ~( ( (& I_n[8:7]) & (~I_n[6] || ~I_n[5]) )
                || ( (& I_n[8:3])) & (~I_n[2] || ~I_n[1]) );

assign Y_n[0] = ~(~I_n[8] 
                || ( (& I_n[8:7]) & ~I_n[6] )
                || ( (& I_n[8:5]) & ~I_n[4] )  
                || ( (& I_n[8:3]) & ~I_n[2] ) 
                || ( (& I_n[8:1]) & ~I_n[0] ) );        

end


    

endmodule