题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
    
    reg [2:0] cnt;
    
    // 实现一
//     always @ (posedge clk or negedge rst_n) begin
//         if(~rst_n) begin
//             cnt <= 0;
//             data <= 0;
//         end
//         else if(cnt == 5) begin
//             cnt <= 0;
//             data <= 1;
//         end
//         else if(cnt == 4) begin
//             cnt <= cnt + 1;
//             data <= 1;
//         end
//         else if(cnt == 3) begin
//             cnt <= cnt + 1;
//             data <= 0;
//         end
//         else if(cnt == 2) begin
//             cnt <= cnt + 1;
//             data <= 1;
//         end
//         else if(cnt == 1) begin
//             cnt <= cnt + 1;
//             data <= 0;
//         end
//         else if(cnt == 0) begin
//             cnt <= cnt + 1;
//             data <= 0;
//         end
//     end
    
    
    //实现二
//     always @ (posedge clk or negedge rst_n) begin
//         if(~rst_n) begin
//             cnt <= 0;
//         end
//         else if(cnt == 6) begin
//             cnt <= 1;
//         end 
//         else
//             cnt <= cnt + 1;
//     end
    
//     always @(*) begin
//         case(cnt)
//             3'd0: data = 0;
//             3'd1: data = 0;
//             3'd2: data = 0;
//             3'd3: data = 1;
//             3'd4: data = 0;
//             3'd5: data = 1;
//             3'd6: data = 1;
//             default:data = data;
//         endcase
//     end
    
    //实现三
    
    reg [5:0] data_r = 6'b001011;
    
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)
            data <= 0;
        else begin
            data <= data_r[5];
            data_r <= {data_r[4:0], data_r[5]};
        end
    end
    
    
    
    
endmodule