`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); reg [2:0]c_state; reg [2:0]n_state; reg [2:0]cnt; parameter cnt_max = 3'd6; always@(posedge clk or negedge rst_n) begin if(!rst_n) c_state <= 3'd0; else c_s...