`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [8:0] vector; always @(posedge clk or negedge rst_n) begin if (! rst_n) begin vector <= 8'd0; end else vector[8:0] <= {vector[7:0], a}; end always @(posedge clk or negedge ...