`timescale 1ns/1ns module data_cal( input clk, input rst, input [15:0]d, input [1:0]sel, output reg [4:0]out, output reg validout ); //*************code***********// reg [15:0] val_tmp; always @(posedge clk or negedge rst) begin if(~rst) begin out <= 5'b00000; validout <...