题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output reg [4:0]out,
output reg validout
);
//*************code***********//

reg [15:0] val_tmp;

always @(posedge clk or negedge rst) begin
    if(~rst) begin
        out <= 5'b00000;
        validout <= 0;
    end
    else begin
        case(sel)
            0: begin val_tmp <= d; validout <= 0; out <= 5'b00000; end
            1: begin out <= val_tmp[3:0] + val_tmp[7:4]; validout <= 1; end
            2: begin out <= val_tmp[3:0] + val_tmp[11:8]; validout <= 1; end
            3: begin out <= val_tmp[3:0] + val_tmp[15:12]; validout <= 1; end
        endcase
    end
end

//*************code***********//
endmodule