`timescale 1ns/1ns module ali16( input clk, input rst_n, input d, output reg dout ); //*************code***********// reg rst_n_d1,rst_n_d2; always@(posedge clk or negedge rst_n) begin if(!rst_n) {rst_n_d2,rst_n_d1}<=0; else {rst_n_d2,rst_n_d1}<={rst_n_d1,1'b1}; e...