题解 | #时钟切换#

`timescale 1ns/1ns

module huawei6(
	input wire clk0  ,
	input wire clk1  ,
	input wire rst  ,
	input wire sel ,
	output reg clk_out
);
//*************code***********//

reg rst_d1=0;
reg rst_d2=0;
always@(posedge clk0)
begin
	if(!rst)
		{rst_d2,rst_d1}<=0;
	else
		{rst_d2,rst_d1}<={rst_d1,rst};
end

//latch 
reg sel_latch;
always@(*)
begin
	if(!rst_d1)
		sel_latch=0;
	else if(!clk0 || (!clk1 && sel==1))
		sel_latch=sel;
	else
		sel_latch=sel_latch;
end

reg sel_latch_d1,sel_latch_d2,sel_latch_d3;
always@(negedge clk0 , negedge rst_d1)
begin
	if(!rst_d1)
		{sel_latch_d1,sel_latch_d2,sel_latch_d3}<=0;
	else
		{sel_latch_d1,sel_latch_d2,sel_latch_d3}<={sel_latch,sel_latch_d1,sel_latch_d2};
end

reg en,en_d1,en_d2,en_d3;
always@(posedge clk0 , negedge rst_d1)
begin
	if(!rst_d1)
		en<=0;
	else if(sel_latch_d1)
		en<=sel_latch;
end

always@(posedge clk1 , negedge rst_d1)
begin
	if(!rst_d1)
		en_d1<=0;
	else
		en_d1<=en;
end


always@(posedge clk1 , negedge rst_d1)
begin
	if(!rst_d1)
		en_d2<=0;
	else
		en_d2<=en_d1;
end

always@(posedge clk1 , negedge rst_d1)
begin
	if(!rst_d1)
		en_d3<=0;
	else
		en_d3<=en_d3;
end



always@(*)
begin
	if(!rst_d2 || (sel_latch_d2 && !sel_latch_d1 ))
		clk_out=0;
	else if(!sel_latch_d1)
		clk_out=clk0;
	else if(en_d3 || (en_d2 && sel_latch_d2) || (en_d1 && clk0))
		clk_out=clk1;
	else
		clk_out=0;
end

//*************code***********//
endmodule