`timescale 1ns/1ns module width_24to128( input clk , input rst_n , input valid_in , input [23:0] data_in , output reg valid_out , output reg [127:0] data_out ); reg[3:0] cnt; always @(posedge clk or negedge rst_n) begin if(!rst_n) cnt <= 4'b0; else begin cnt...