`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, input data_valid, output reg match ); reg [3:0] data_r; always @ (posedge clk or negedge rst_n) if (!rst_n) data_r <= 3'b1111; else if (data_valid) data_r <= {data_r[2:0],data}; els...