题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);
	reg [5:0] ref;
	always @ (posedge clk or negedge rst_n)
		if (!rst_n)
			ref <= 6'b001011;
		else
			ref <= {ref[4:0],ref[5]};
	always @ (posedge clk or negedge rst_n)
		if (!rst_n)
			data <= 0;
		else
			data <= ref[5];
						
endmodule