题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
	localparam S_IDLE = 3'd0;
	localparam S_0    = 3'd1;
	localparam S_01   = 3'd2;
	localparam S_011  = 3'd3;
	localparam S_0111 = 3'd4;
	localparam S_01110 = 3'd5;
	localparam S_011100 = 3'd6;
	localparam S_0111000 = 3'd7;
	 
	reg [2:0] state , nextstate;

	always@(posedge clk or negedge rst_n) begin
		if (!rst_n ) state <= S_IDLE;
		else state <= nextstate;
	end

	always@(*) begin
		case (state) 
		S_IDLE : begin
			if (a) nextstate = S_IDLE;
			else nextstate  = S_0;
		end
		S_0 : begin
			if (a) nextstate = S_01;
			else nextstate = S_0;
		end
		S_01: begin
			if (a) nextstate = S_011;
			else nextstate = S_0;
		end
		S_011:begin
			if (a) nextstate = S_0111;
			else nextstate = S_0;
		end
		S_0111: begin
			if (a) nextstate = S_IDLE;
			else nextstate = S_01110;
		end
		S_01110 : begin
			if (a) nextstate = S_01;
			else nextstate = S_011100;
		end
		S_011100 : begin
			if (a) nextstate = S_01;
			else nextstate = S_0111000;
		end
		S_0111000: begin 
			if (a) nextstate = S_01;
			else nextstate = S_0; 
		end
		default begin 
			nextstate <= S_IDLE;
		end
		endcase
	end
	reg matchin ;
	always @(posedge clk or negedge rst_n) begin
		if ( !rst_n) begin
			match <= 0;
			matchin <=0;
		end
		else begin 
			match <= matchin;
			if (state == S_0111000 && a) begin
				matchin <= 1;
			end
			else begin 
				matchin <= 0;
			end
		end
	end

  
endmodule

饿，这里写成melay型状态机了，所以最先一直跑不对，后边内部加一个打一拍就好了。