题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
);
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;

reg [2:0] state;
reg [2:0] next_state;

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    state <= S0;
  else
    state <= next_state;
end

always@(*)begin
  if(data_valid)begin
    case(state)
	  S0:next_state = (!data)?S1:S0;
      S1:next_state = (data)?S2:S1;
      S2:next_state = (data)?S3:S1;
      S3:next_state = (!data)?S4:S0;
      S4:next_state = (!data)?S1:S0;
	  default:next_state = S0;
	endcase
  end
  else begin
    if(state == S4)//增加清零功能，确保match信号是一个持续一个时钟周期的脉冲信号
	  next_state = S0;
	else
	  next_state = next_state;
  end
end

always@(posedge clk or negedge rst_n)begin
  if(!rst_n)
    match <= 1'b0;
  else 
    match <= (next_state == S4)?1'b1:1'b0;
end


  
endmodule