题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);
    wire c2 = ((A_in[0] ^ B_in[0] )& C_1) | (A_in[0]&B_in[0]);
	wire c3 = ((A_in[1] ^ B_in[1]) & c2) | (A_in[1] & B_in[1]);
	wire c4 = ((A_in[2] ^ B_in[2] )& c3) |  (A_in[2] & B_in[2]);
	assign  CO = ((A_in[3] ^ B_in[3]) & c4) |  (A_in[3] & B_in[3]);

	assign S = {(A_in[3] ^ B_in[3]) ^ c4,(A_in[2] ^ B_in[2]) ^ c3,(A_in[1] ^ B_in[1]) ^ c2,(A_in[0] ^ B_in[0]) ^ C_1};

endmodule