题解 | #脉冲同步器（快到慢）#

`timescale 100ps/100ps

module pulse_detect(
	input 				clka	, 
	input 				clkb	,   
	input 				rst_n		,
	input				sig_a		,

	output  		 	sig_b
);

reg toggle,q1,A,B;

always @ (posedge clka or negedge rst_n) begin
	if (~rst_n)
	  toggle <= 1'b0;
	else if (sig_a)
	  toggle <= ~toggle;
end

always @ (posedge clkb or negedge rst_n) begin
	if (~rst_n) begin
		q1 <= 1'b0;
		A <= 1'b0;
		B <= 1'b0;
	end
	else begin
		q1 <= toggle;
		A <= q1;
		B <= A;
	end
end

assign sig_b = A ^ B;

endmodule