题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
	reg	[7:0]	data;
	reg	[2:0]	bit_cnt;
	reg	flag;

always@(posedge clk  or negedge rst_n)
	if(!rst_n)
		bit_cnt	<=	3'd0;
	else
		bit_cnt	<=	bit_cnt	+ 1'b1;

always@(posedge clk  or negedge rst_n)
	if(!rst_n)
		flag	<=	1'b0;
	else	if(bit_cnt == 3'd7)
		flag	<=	1'b1;
	else
		flag	<=	1'b0;

always@(posedge clk or negedge rst_n)
	if(!rst_n)
		data	<=	8'd0;
	else
		data[7-bit_cnt] <=	a;
	
always@(posedge clk or negedge rst_n)
	if(!rst_n)
		match	<=	1'b0;
	else	if(flag && data==8'b0111_0001)
		match	<=	1'b1;
	else
		match	<=	1'b0;
endmodule