题解 | #单端口RAM#

`timescale 1ns/1ns

module RAM_1port(
    input clk,
    input rst,
    input enb,
    input [6:0]addr,
    input [3:0]w_data,
    output wire [3:0]r_data
);
reg [3:0]   ram [127:0];
//write
integer i;
always@(posedge clk or negedge rst)
    if(!rst)
        begin
            for(i=0;i<128;i=i+1)
                ram[i]  <=  4'd0;
        end
    else    if(enb)
            ram[addr]   <=  w_data;

//read

assign  r_data  = (!enb)? ram[addr]:4'd0;
endmodule