题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter IDLE = 0;
parameter SECOND = 1;
parameter THIRD	 = 2 ;
parameter FOURTH = 3 ;
parameter FIFTH  = 4 ;
parameter LAST   = 5 ;
reg			[2:0]		cur_state ;
reg			[2:0]		next_state;
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		cur_state <= IDLE ;
	end
	else begin
		cur_state <= next_state ;
	end
end
always @(*) begin
	case(cur_state)
		IDLE: begin
			if(data) begin
				next_state = SECOND ;
			end
			else begin
				next_state = IDLE ;
			end
		end
		SECOND: begin
			if(!data) begin
				next_state = THIRD ;
			end
			else begin
				next_state = SECOND ;
			end
		end
		THIRD: begin
			if(data) begin
				next_state = FOURTH ;
			end
			else begin
				next_state = IDLE ;
			end
		end	
		FOURTH: begin
			if(data) begin
				next_state = LAST ;
			end
			else begin
				next_state = THIRD ;
			end
		end		
		LAST: begin
			if(data) begin
				next_state = SECOND ;
			end
			else begin
				next_state = THIRD ;
			end
		end	
	endcase
end
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		flag <= 1'b0 ;
	end
	else if(cur_state==LAST ) begin
		flag <= 1'b1 ;
	end
	else begin
		flag <= 1'b0 ;
	end
end

//*************code***********//
endmodule