题解 | #格雷码计数器#

module gray_counter(
   input   clk,
   input   rst_n,
   output  reg [3:0] gray_out
);
reg[3:0] count;
reg clk_2;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
clk_2=1'b0;
end
else
begin
clk_2<=~clk_2;
end
end
always @(posedge clk_2 or negedge rst_n)
begin
if(!rst_n)
begin
count<=4'd0;
end
else
begin
count<=count+4'd1;
end
end

always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
gray_out<=4'd0;
end
else
begin
gray_out[3]=count[3];
gray_out[2]=count[3]^count[2];
gray_out[1]=count[2]^count[1];
gray_out[0]=count[1]^count[0];
end
end
endmodule