题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
	reg [3:0] ram[7:0];
	integer i;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
for (i=0;i<8;i=i+1)
begin
ram[i]<=0;
end
read_data<=0;
end
	else
	begin
	ram[write_addr]<= write_en ? write_data : ram[write_addr];
	read_data<= read_en ? ram[read_addr] : 4'd0; 
	end
end
endmodule