题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [2:0] cnt;
reg [5:0] data_reg;


always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
 		ready_a=1'b0;
	else
	    ready_a=1'b1;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		cnt<= 3'd0;
	else if(valid_a && ready_a)begin
		if(cnt==3'd5)
			cnt <= 3'd0;
		else
			cnt<=  cnt + 1'b1;
		end
	else
		cnt <=  cnt;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		valid_b <=  1'd0;
	else if(cnt==3'd5&& valid_a && ready_a)
		valid_b <=  1'd1;
	else
		valid_b <=  1'd0;
end


always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_reg <=  6'd0;
	else if(valid_a && ready_a)
		data_reg <=  {data_a,data_reg[5:1]};
	else
		data_reg <=  data_reg;
		
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_b <=  6'd0;
	else if(valid_a && ready_a&&cnt==3'd5)
		data_b <=  {data_a,data_reg[5:1]};
	else
		data_b<=  data_b;
end


endmodule