题解 | #输入序列连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
reg[3:0] current_state,next_state;
parameter s0=4'd0;
parameter s1=4'd1;
parameter s2=4'd2;
parameter s3=4'd3;
parameter s4=4'd4;
parameter s5=4'd5;
parameter s6=4'd6;
parameter s7=4'd7;
parameter s8=4'd8;

always @(*)

begin
case(current_state)
s0:next_state<=a?s0:s1;
s1:next_state<=a?s2:s1;
s2:next_state<=a?s3:s1;
s3:next_state<=a?s4:s1;
s4:next_state<=a?s0:s5;
s5:next_state<=a?s2:s6;
s6:next_state<=a?s2:s7;
s7:next_state<=a?s8:s1;
  default:next_state<=s0;
endcase
end


always@(posedge clk or negedge rst_n )
begin
if(!rst_n)
begin
current_state<=s0;
end
else
begin
current_state<=next_state;
end
end

always@(posedge clk or negedge rst_n )
begin
if(!rst_n)
begin
match<=1'b0;
end
else
begin
if(current_state==s8)
begin
match<=1'b1;
	end
	else
	begin
match<=1'b0;
	end
end
end


endmodule