题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg [15:0]temp;
reg [4:0] t_out;
reg flag=1'b0,v_out;
always@(posedge clk or rst)
begin
if(!rst)
begin
v_out<=1'b0;
t_out<=1'b0;
end
else
begin
   if(sel==2'b00)
   begin
   v_out<=0; 
   t_out<=0;
   flag<=0;
   temp<=d;
   end
        else
        begin
         v_out<=1;
         flag<=1;  
         case(sel)
2'b01:begin t_out<=temp[3:0]+temp[7:4] ;end
2'b10:begin t_out<=temp[3:0]+temp[11:8] ;end
2'b11:begin t_out<=temp[3:0]+temp[15:12] ;end
default: begin t_out<=0;  end
endcase
 
        end
end
end










assign validout=v_out;
assign out=t_out;
//*************code***********//
endmodule