题解 | #多功能数据处理器#

有符号数的操作

`timescale 1ns/1ns
module data_select(
	input clk,
	input rst_n,
	input signed[7:0]a,//有符号数的定义
	input signed[7:0]b,
	input [1:0]select,
	output reg signed [8:0]c
);

always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
		c <= 9'd0; 
	end
	else begin
		case(select)
		2'd0:begin
			c <= a; 
		end
		2'd1:begin
			c <= b;
		end
		2'd2:begin
			c <= a + b; 
		end
		2'd3:begin
			c <= a - b; 
		end
		endcase
	end
endmodule