题解 | #含有无关项的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

reg [8:0] a_temp;

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		a_temp<=9'b0;
	end
	else begin
		a_temp<={a_temp[7:0],a};
	end
end

always @ (posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		match<=1'b0;
	end
	else begin
		if(a_temp[8:6]==3'b011 & a_temp[2:0]==3'b110) begin
			match<=1'b1;
		end
		else begin
			match<=1'b0;
		end
	end
end
///////////////由于含有无关项，并且还要检测重复序列，因此用状态机法很难进行操作。
// parameter idle=4'd0,s1=4'd1,s2=4'd2,s3=4'd3,s4=4'd4,s5=4'd5,s6=4'd6,s7=4'd7,s8=4'd8,s9=4'd9;
// reg [3:0] state,next;

// always @ (posedge clk or negedge rst_n) begin
// 	if(~rst_n) begin
// 		state<=idle;
// 	end
// 	else begin
// 		state<=next;
// 	end
// end

// always @(*) begin
// 	case(state) begin
// 		idle:next=a?idle:s1;
// 		s1:  next=a?s2:s1;
// 		s2:  next=a?s3:s1;
// 		s3:  next=s4;
// 		s4:  next=s5;
// 		s5:  next=s6;
// 		s6:  next=a?s7:s1;
// 		s7:  next=a?s8:s1;
// 		s8:  next=a?


// always @(posedge clk or negedge rst_n) begin
// 	if(~rst_n)
		
  
endmodule