题解 | #简易秒表#
简易秒表
https://www.nowcoder.com/practice/6493ca8c7b67499f918e1fa33b4cdeda
`timescale 1ns/1ns
module count_module(
input clk,
input rst_n,
output reg [5:0]second,
output reg [5:0]minute
);
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
second <= 0;
minute <= 0;
end
else begin
second <= (&minute[5:2])? 0 :
(&second[5:2])? 1 : second + 1;
minute <= (&minute[5:2])? minute :
(&second[5:2])? minute + 1 : minute;
end
end
endmodule
投递华为等公司8个岗位 >
，唯一的解就是行业好起来
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