题解 | #脉冲同步电路#

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output  		 	dataout
);
	reg data_in_fast;
	reg data_in_sr1,data_in_sr2,data_in_sr3;

	always @(posedge clk_fast or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_in_fast <= 1'b0;
		else if(data_in)
		    data_in_fast = ~data_in_fast;
		else
		    data_in_fast = data_in_fast;		
	end

	always @(posedge clk_slow or negedge rst_n) begin
		if(rst_n == 1'b0)begin
			data_in_sr1 <= 1'b0;
			data_in_sr2 <= 1'b0;
			data_in_sr3 <= 1'b0;
		end
		else begin
			data_in_sr1 <= data_in_fast;
			data_in_sr2 <= data_in_sr1;
			data_in_sr3 <= data_in_sr2;
		end
	end

	assign dataout = data_in_sr3 ^ data_in_sr2;



endmodule

异或：同时检测上升沿 下降沿。