题解 | #数据串转并电路#
数据串转并电路
https://www.nowcoder.com/practice/6134dc3c8d0741d08eb522542913583d
串转并那就设置一个寄存器data_reg寄存，并设置一个0~5的计数器cnt控制，在ready_a和valid_a有效时，0~4时寄存，5时用拼接运算符完成data_b输出，无效时则都维持不变。其实还算是一个挺简单的题目，不过我一开始在看时序图时以为第二次data_b输出的最低为采集的是画圈位置的data，误以为图有误，与群里老哥聊过后明白了：在输出data_b时只要eady_a和valid_a有效也会采集data。所以最低位是在第一次data_b输出时采集的data。
`timescale 1ns/1ns
module s_to_p(
input clk ,
input rst_n ,
input valid_a ,
input data_a ,
output reg ready_a ,
output reg valid_b ,
output reg [5:0] data_b
);
reg [2:0] cnt;
reg [4:0] data_reg;
always@(posedge clk,negedge rst_n)begin
if(!rst_n)
ready_a <= 1'b0;
else
ready_a <= 1'b1;
end
always@(posedge clk,negedge rst_n)begin
if(!rst_n)
cnt <= 3'd0;
else if(valid_a && ready_a)begin
if(cnt == 3'd5)
cnt <= 3'd0;
else
cnt <= cnt + 1'b1;
end
else
cnt <= cnt;
end
always@(posedge clk,negedge rst_n)begin
if(!rst_n) begin
data_reg <= 4'd0;
data_b <= 5'd0;
end
else if(valid_a && ready_a)
case(cnt)
3'd0: data_reg[0] <= data_a;
3'd1: data_reg[1] <= data_a;
3'd2: data_reg[2] <= data_a;
3'd3: data_reg[3] <= data_a;
3'd4: data_reg[4] <= data_a;
3'd5: data_b <= {data_a,data_reg};
default:;
endcase
else
data_reg <= data_reg;
end
always@(posedge clk,negedge rst_n)begin
if(!rst_n)
valid_b <= 1'b0;
else if(valid_a && ready_a && cnt == 3'd5)
valid_b <= 1'b1;
else
valid_b <= 1'b0;
end
endmodule
