题解 | #状态机-非重叠的序列检测#

`timescale 1ns/1ns

module sequence_test1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
    parameter S0 = 3'd0;
    parameter S1 = 3'd1;
    parameter S2 = 3'd2;
    parameter S3 = 3'd3;
    parameter S4 = 3'd4;
    reg [2:0] cstate, nstate;
    always@(posedge clk or negedge rst) begin
        if(!rst) begin
            cstate <= S0;
        end
        else begin
            cstate <= nstate;
        end
    end
    always@(*) begin
        case(cstate)
            S0: begin
                nstate = data?S1:S0;
            end
            S1: begin
                nstate = data?S1:S2;
            end
            S2: begin
                nstate = data?S3:S0;
            end
            S3: begin
                nstate = data?S4:S2;
            end
            S4: begin
                nstate = data?S0:S2;
            end
            default: begin
                nstate = S0;
            end
        endcase
    end
    always@(posedge clk or negedge rst) begin
        if(!rst) begin
            flag <= 1'b0;
        end
        else begin
            flag <= data&(cstate==S4);
        end
    end
endmodule