题解 | #时钟分频（偶数）#
时钟分频（偶数）
https://www.nowcoder.com/practice/49a7277c203a4ddd956fa385e687a72e
//解法1： `timescale 1ns/1ns module even_div ( input wire rst , input wire clk_in, output wire clk_out2, output wire clk_out4, output wire clk_out8 ); //*************code***********// reg [2:0] cnt; reg clk_out2_r, clk_out4_r, clk_out8_r; always @ (posedge clk_in, negedge rst) begin if(~rst) begin cnt <= 3'b0; end else begin cnt <= (cnt == 3'd7) ? 3'd0 : cnt + 3'd1; end end always @ (posedge clk_in, negedge rst) begin if(~rst) begin clk_out2_r <= 1'b0; end else begin clk_out2_r <= ~clk_out2_r; end end assign clk_out2 = clk_out2_r; always @ (posedge clk_in, negedge rst) begin if(~rst) begin clk_out4_r <= 1'b0; end else if (cnt % 2 == 1'b0) begin clk_out4_r <= ~clk_out4_r; end end assign clk_out4 = clk_out4_r; always @ (posedge clk_in, negedge rst) begin if(~rst) begin clk_out8_r <= 1'b0; end else begin clk_out8_r <= ((cnt == 3'd4) || (cnt == 3'd0)) ? (~clk_out8_r) : clk_out8_r; end end assign clk_out8 = clk_out8_r; //*************code***********// endmodule自己解法，偶数分频，0和n/2开始翻转，
解法2：
`timescale 1ns/1ns module even_div ( input wire rst , input wire clk_in, output wire clk_out2, output wire clk_out4, output wire clk_out8 ); //*************code***********// reg clk_out2_r, clk_out4_r, clk_out8_r; always@(posedge clk_in or negedge rst) begin if(~rst) clk_out2_r <= 0; else clk_out2_r <= ~clk_out2_r; end always@(posedge clk_out2 or negedge rst) begin if(~rst) clk_out4_r <= 0; else clk_out4_r <= ~clk_out4_r; end always@(posedge clk_out4 or negedge rst) begin if(~rst) clk_out8_r <= 0; else clk_out8_r <= ~clk_out8_r; end assign clk_out2 = clk_out2_r; assign clk_out4 = clk_out4_r; assign clk_out8 = clk_out8_r; //*************code***********// endmodule
