题解 | #Johnson Counter#

用状态机来做

`timescale 1ns/1ns

module JC_counter(
   input                clk ,
   input                rst_n,
 
   output reg [3:0]     Q  
);
    parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7;
    reg [2:0] state,nextstate;
    
    always@(posedge clk or negedge rst_n)
        if(!rst_n) state<=0;
    else state<=nextstate;
    
    always@(*)
        case(state) 
            s0:nextstate<=s1;
            s1:nextstate<=s2;
            s2:nextstate<=s3;
            s3:nextstate<=s4;
            s4:nextstate<=s5;
            s5:nextstate<=s6;
            s6:nextstate<=s7;
            s7:nextstate<=s0;
            default:nextstate<=s0;
       endcase
    
        always@(*)
        case(state) 
            s0:Q<=4'b0000;
            s1:Q<=4'b1000;
            s2:Q<=4'b1100;
            s3:Q<=4'b1110;
            s4:Q<=4'b1111;
            s5:Q<=4'b0111;
            s6:Q<=4'b0011;
            s7:Q<=4'b0001;
            default:Q<=4'b0000;
       endcase
    
endmodule