题解 | #含有无关项的序列检测#

`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input a, output reg match ); reg [8:0] trans;

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        trans<=0;
    end
    else begin
        trans<={trans[7:0],a};
    end
end

always @(posedge clk or negedge rst_n)begin
    if(~rst_n)begin
        match<=0;
    end
    else begin
        match<=(trans[8:6]==3'b011)&(trans[2:0]==3'b110);
    end
end
    

endmodule