题解 | #数据累加输出#

1. 测试用例data_out随输入改变，题目没有画完整
2. ready_a 有效在valid_b无效或ready_b有效时，才能保证不会浪费下一级握手的哪一个周期时间。（即与下一级握手的周期也完成了与上一级的握手）

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);
    //defiantion
    reg [1 : 0] cnt;
    wire add_cnt;
    wire end_cnt;
    reg ready_a_r;
    
    //output 
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) data_out <= 10'd0;
        else if(add_cnt && cnt == 0) data_out <= data_in;
        else if(add_cnt) data_out <= data_out + data_in;
    end
    
    assign add_cnt = ready_a && valid_a;
    assign end_cnt = add_cnt && (cnt == 3);
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) cnt <= 'd0;
        else if(end_cnt) cnt <= 'd0;
        else if(add_cnt) cnt <= cnt + 1'b1;
    end
    
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) valid_b <= 'd0;
        else if(end_cnt) valid_b <= 1'b1;
        else if(ready_b) valid_b <= 1'b0;
    end    
    
    assign ready_a = !valid_b | ready_b;
endmodule