`timescale 1ns/1ns module seller1( input wire clk , input wire rst , input wire d1 , input wire d2 , input wire d3 , output reg out1, output reg [1:0]out2 ); //*************code***********// reg [2:0]sum; always@( clk or negedge rst)begin if(!rst) sum <= 3'd0; else sum <= (out...