`timescale 1ns/1ns module multi_sel( input [7:0]d, input clk, input rst, output reg input_grant, output reg [10:0]out ); //*************code***********// reg [1:0] cnt; reg [7:0] d_tmp; initial begin input_grant = 1'b0; out = 10'b0; end always@(posedge clk) begin if(!rst) begin ...
