`timescale 1ns/1ns module rom( input clk, input rst_n, input [7:0]addr, output [3:0]data ); wire [3:0] rom_data [7:0] ; genvar i ; generate for(i=0; i<8; i=i+1) begin : initial_0 assign rom_data[i] = 2*i ; end endgenerate assign data = rom_data[addr] ; endmodule