`timescale 1ns/1ns module mux4_1( input [1:0]d1,d2,d3,d0, input [1:0]sel, output[1:0]mux_out ); //*************code***********// assign mux_out = (sel>2'b10)?d0:((sel>2'b01)?d1:(sel>2'b00)?d2:d3); //*************code***********// endmodule