`timescale 1ns/1ns module mux4_1( input [1:0]d1,d2,d3,d0, input [1:0]sel, output[1:0]mux_out ); //*************code***********// reg mux_out; always @(*) begin case(sel) 'b00: mux_out = d3; 'b01: mux_out = d2; 'b10: mux_out = d...